1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to MOS-FET including raised source and drain layers and a particular shaped insulating film formed on a sidewall of a gate electrode, and a method of fabricating the same.
2. Description of the Related Art
Fabrication of a transistor in a smaller size is absolutely necessary for operating a MOS integrated circuit at higher speed and densifying MOS integrated circuit. However, formation of a MOS transistor in a smaller size is accompanied with problems such as short channel effect and punch-through.
To solve those problems, Japanese Unexamined Patent Publication No. 2-222153, based on U.S. patent application Ser. No. 289,346 filed on Dec. 22, 1988 by Mark S. Rodder et al. and assigned to Texas Instrument Incorporated, has suggested a method of forming raised source and drain layers on a silicon substrate. The suggested method is explained hereinbelow with reference to FIGS. 1A to 1C.
As illustrated in FIG. 1A, local oxidation is carried out on a silicon substrate 1A to thereby form device isolation layers 2 for defining device formation regions therebetween. Then, n- or p-type impurities are ion-implanted into the p- or n-type silicon substrate 1A at a depth of a couple of micrometers (.mu.m), followed by rapid thermal annealing (RTA) at about 850 degrees centigrade for activation of the impurities. Thus, a well region 1B is formed. After impurities have been implanted for controlling a threshold value of a transistor, a gate oxide film 3 is formed on the silicon substrate 1A by 5 nm, and a polysilicon film which will later make a gate electrode 4 is deposited on the gate oxide film 3 by 200 nm, and further an oxide film is deposited on the polysilicon film by 50 nm. Then, the gate oxide film, the polysilicon film and the oxide film are patterned to thereby form the gate electrode 4 on the gate oxide film 3, and the oxide film 5A on the gate electrode 4. Then, a nitride film is deposited over a resultant by 20 nm, followed by plasma etching to remove unnecessary portions of the nitride film and form a first gate electrode sidewall 16A.
Then, as illustrated in FIG. 1B, a resultant is treated with vapor of hydrofluoric acid to thereby remove natural oxide films formed on regions of the silicon substrate 1A where source and drain regions are later to be formed. Then, a resultant is introduced without exposing to atmosphere into an apparatus for accomplishing a low pressure chemical vapor deposition (LPCVD), in which selective epitaxial growth is accomplished at about 800 degrees centigrade on regions of the silicon substrate 1A where silicon is exposed, employing dichlorosilane (SiCl.sub.2 H.sub.2) as a source gas which is mixed with hydrogen chloride (HCl) gas under a condition that a silicon film is not formed on the silicon oxide films 2 and 5A. As a result, there are formed raised source and drain layers 7A between the device isolation layers 2 and the first gate electrode sidewalls 16A. There are formed gaps between the first gate electrode sidewalls 16A and facets 8A and 8B of the raised source and drain regions 7A. Herein, the facets 8A and 8B are inclined portions of the raised source and drain layers 7A at which the raised source and drain layers 7A do not make close contact with the first gate electrode sidewalls 16A. Thus, it is necessary to form second sidewalls over the first gate electrode sidewalls 16A in order to fill the thus formed gaps therewith. The facet 8A is a plane having Miller indices (111), whereas the facet 8B is a plane having high Miller indices such as (311) and (511).
An oxide film is deposited over a resultant by about 40 nm. Then, the thus deposited oxide film is plasma-etched so that a portion thereof making contact the first gate electrode sidewall 16A remains unetched and the rest thereof is removed. Thus, there are formed second gate electrode sidewalls 16B entirely covering the facets 8A and partially covering the facets 8B therewith.
Then, after the oxide film 5A located on the gate electrode 4 is removed, the gate electrode 4 is oxidized at an exposed surface thereof to thereby form a thin film having a depth of about 5 nm. This film prevents the gate electrode 4 and source/drain regions from being contaminated by ion implantation to be carried out in a next step. Then, BF.sub.2 is ion-implanted into the raised source and drain layers 7A at 10-20 KeV when the raised source and drain layers 7A is p-type, or As is ion-implanted into the raised source and drain layers 7A at 40-60 KeV when the raised source and drain layers 7A is n-type, followed by RTA at about 1000 degrees centigrade to thereby diffuse and activate the impurities into the silicon substrate 1A and the gate electrode 4. Thus, there are formed source and drain diffusion layers 9 in the silicon substrate 1A.
As illustrated in FIG. 1C, after the thin film for prevention of the gate electrode 4 and source/drain regions from contamination due to the ion-implantation is removed, titanium is sputtered over a resultant by about 40 nm, followed by RTA at about 700 degrees centigrade to thereby form a titanium silicide (TiSi2) layer 10 (indicated with reference numerals 10A and 10B in FIG. 1C) on the raised source and drain layers 7A and the gate electrode 4. The thus formed titanium silicide 10 has a relatively high resistance. Then, unnecessary layers which have been formed at the same time when the titanium silicide layer 10 has been formed, such as titanium nitride and extra titanium, are selectively removed by etching, followed by RTA at about 850 degrees centigrade to thereby make the titanium silicide layer 10 lower in resistance. Thus, there are formed low-resistive titanium silicide layers 10A and 10B, and the silicidation process is completed.
Then, an interlayer insulating film 11 is deposited over a resultant at low temperature by plasma enhanced CVD. Contact holes 12 are formed leading to the titanium silicide layers 10A and 10B and hence the source and drain layers 9. Then, aluminum electrodes 13 are formed filling the contact holes 12 therewith. Thus, there is completed a MOS transistor.
As illustrated in FIG. 1B, a junction depth X of source and drain diffusion layers is defined as a depth from an upper surface of a channel formation region to pn junction. Accordingly, a transistor having raised source and drain diffusion layers such as those indicated with reference numeral 7A can have a shallower junction depth by a thickness of raised source and drain layers than a transistor having no raised source and drain layers. Namely, the formation of raised source and drain layers provides an advantage that a shallow diffusion layer is able to be readily formed.
For instance, when a diffusion layer having a depth of 100 nm is to be formed by introduction of impurities due to ion-implantation and activation by RTA, if raised source and drain layers are formed by a 50 nm thickness, it is allowed for the diffusion layer to have just a depth of 50 nm. Hence, it is possible to form a diffusion layer suitable for a fine MOS transistor of 0.25 .mu.m design rule or smaller. In addition, it is also possible to prevent sheet and contact resistance of source and drain regions from becoming higher in dependence on a thickness of raised source and drain layers.
As mentioned earlier with reference to FIG. 1C, when the raised source and drain layers 7A are formed by selective growth of silicon films, there may be formed the facets 8A and 8B at which the raised source and drain layers 7A do not make close contact with the first gate electrode sidewalls 16A. Since the diffusion layers 9 are formed by ion-implantation after the second gate electrode sidewalls 16B have been formed, a junction depth of the diffusion layers 9 is influenced by the facets 8A and 8B of the second gate electrode sidewalls.
The reason why the facets 8A and 8B are formed while the selective growth of the silicon films is that silicon atoms existing at an outer surface of silicon films move to a plane having smaller free energy so that free energy of entirety of the silicon films is minimized. It is said that (100), (110), (311) and (111) planes of a silicon dioxide film (or a silicon nitride film) have free energy smaller in this order. With a greater thickness of the raised source and drain layers 7A, silicon atoms are diffused from the first gate electrode sidewalls 16A to a surface of the raised source and drain layers 7A having smaller free energy to thereby form planes having smaller free energy, such as a (111) plane. Namely, the raised source and drain layers 7A grow so that a film which will make contact with the first gate electrode sidewalls 16A has a minimum thickness and thus the raised source and drain layers 7A have minimum free energy, and as a result there are formed facets such as those indicated with reference numerals 8A and 8B.
Once facets have started to be formed, resultant facets have a shape determined in accordance with growth rate of each of facets. In the above mentioned case, since a (311) plane has smaller growth rate than other planes, if a (311) plane has once started to be formed, the (311) plane continues to expand, and as a result, a resultant facet horizontally expands.
For instance, if a facet has only (111) planes like the facet 8A illustrated in FIG. 1B, the facet makes an angle of about 15 degrees with the first gate electrode sidewalls 16A. Hence, if the raised source and drain layers 7A are designed to have a thickness of about 60 nm, a gap to be formed between the first gate electrode sidewall 16A and the facet 8A is about 16 nm in width (60 nm.times.sin 15.degree..apprxeq.16 nm). Thus, it is relatively easy to completely fill the gap with an insulating film such as the second gate electrode sidewalls 16B. However, most of the cases, there is formed a (311) or (511) plane, in which case the gap formed between the first gate electrode sidewalls 16A and the facet 8A has a width of about 100 nm. Thus, if the gap is completely filled with an insulating film such as the second gate electrode sidewalls 16B, there would be accompanied a problem of generation of parasitic resistance below the first gate electrode sidewalls 16A. This makes a MOS transistor away from practical use.
On the other hand, if only a plane (111) is to be covered with the second gate electrode sidewalls 16B, there would be accompanied a problem that shapes of (311) and (511) planes would exert harmful influence on junction depth of a diffusion layer.
Japanese Unexamined Patent Publication No. 5-182981 has suggested a method of controlling a shape of a facet which makes contact with a first gate electrode sidewalls. In the suggested method, as illustrated in FIG. 2, a first gate electrode sidewall 16C is designed to have a reverse tapered shape. Raised source and drain layers 7B are formed by selective epitaxial growth so that the raised source and drain layers 7B make close contact with the first gate electrode sidewalls 16C without a gap therebetween.
However, when a fine MOS transistor is to be fabricated, it would be quite difficult or almost impossible to form a sidewall with high accuracy such as the first gate electrode sidewall 16C having a reverse tapered shape.
As having been explained so far, it is impossible to completely control a shape of facets in accordance with conventional methods of fabricating a semiconductor device. As a result, a shape of facets has large dispersion that exerts remarkable influence on junction depth of a diffusion layer, resulting in problems of reduction in a fabrication yield and lack of stability in performances of a resultant MOS transistor.
K. Weldon et al. has suggested novel raised source and drain structures which have been fabricated using selective silicon deposition (SSD). According to Abstract No. 478 having been described by them, significant improvements in narrow line salicide formation and salicide-silicon interfacial resistance have been made, and functional 0.40 .mu.m CMOS SRAM devices were fabricated with SSD vs. non-SSD splits showing comparable yield.